In many integrated circuits utilized to provide power for power supplies, driving motors, and the like, two transistors, such as MOS transistors, are connected with the current carrying electrodes in series with a V+ supply connected at one end (one current carrying electrode), ground or the like connected at the other end (the other current carrying electrode) and a terminal at the junction of the two transistors providing an output. A control signal input terminal is connected to the control electrodes of each of the transistors ad ideally causes one transistor to turn on when the other transistor is turned off. The problem with this arrangement is that on occasion both transistors are on simultaneously. This provides a nearly direct short between the V+ supply and ground.
To eliminate this problem, the prior art connects the control signal input terminal directly to the control electrode of one of the transistors and through an inverter to the control electrode of the other transistor. In addition, passive elements such as resistors and capacitors are connected in the circuit to delay the application of the control signal to at least one of the control electrodes. The delay prevents both transistors from being switched simultaneously. In the process of determining the correct amount of delay (the value of the resistors and capacitors) so that both transistors are never turned on simultaneously, variations in estimated capacitance of the power transistors, temperature and the fabrication process itself must be taken into account. Thereby, an extra amount of margin is required in the delay, which greatly effects switching speed. Also, because the above mentioned variables have relatively fixed maximums, it is very difficult to improve switching speed in these prior art circuits.